Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Dual-coupled phase-locked loops for clock and packet-based synchronization

Dual-coupled phase-locked loops for clock and packet-based synchronization

US Patent 9369270 · Granted Jun 14, 2016

Estimated economic value: $9,587,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Cross-coupled timing synchronization platform2025
Dual digital phase lock loop with unmodulation coupling2024
Hitless re-arrangements in coupled digital phase-locked loops2020
Time slotted bus system for multiple coupled digital phase-locked loops2020
Time slotted bus system for multiple coupled digital phase-locked loops2019
Hitless re-arrangements in coupled digital phase-locked loops2019
Methods and apparatus for transmitting data over a clock signal2017
Methods and apparatus for synchronizing operations using separate asynchronous s2016
Phase locked loop fast lock method2008
Digital phase-locked loop with master-slave modes2007
Clock recovery PLL2005
Frequency synthesizer1999