Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Measuring delay between signal edges of different signals using an undersampling clock

Measuring delay between signal edges of different signals using an undersampling clock

US Patent 9344075 · Granted May 17, 2016

Estimated economic value: $1,734,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Clock gating for scan shift clock in a mesh clock environment2025
System and method for performing a failure assessment of an integrated circuit2023
Management system, method and apparatus for licensed delivery and accounting of 2015
Synchronizing TAP controller after power is restored2013
Methods and apparatus for testing delay locked loops and clock skew2010
Method and apparatus for optimized parallel testing and access of electronic cir2009
Method and apparatus for embedded built-in self-test (BIST) of electronic circui2008
System and method for optimized test and configuration throughput of electronic 2008
Methods and apparatus for testing delay locked loops and clock skew2008
Method and apparatus for optimized parallel testing and access of electronic cir2006
Method and apparatus for embedded built-in self-test (BIST) of electronic circui2005
Method and apparatus for providing optimized access to circuits for debug, progr2003