Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Imagers with stacked integrated circuit dies

Imagers with stacked integrated circuit dies

US Patent 9343497 · Granted May 17, 2016

Estimated economic value: $7,688,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Inspection method, substrate processing method including the same, and substrate2025
Image sensor and analog-to-digital converter2023
Integrated fingerprint and force sensor2021
Adaptive reference for differential capacitive measurements2018
Differential readout for sensor array2017
Sensor array with split-drive differential sensing2017
Ramp and successive approximation register analog to digital conversion methods,2016
Offset injection in an analog-to-digital converter2015
Methods and apparatus for performing code correction for hybrid analog-to-digita2013
Variable gain stage having same input capacitance regardless of the stage gain2011
High slew rate amplifier, analog-to-digital converter using same, CMOS imager us2011
Method and apparatus for reducing temporal row-wise noise in imagers2011