Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods

Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods

US Patent 9286257 · Granted Mar 15, 2016

Estimated economic value: $7,157,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Synchronized system-on-chip telemetry aggregation and buffering2025
Providing media power telemetry for virtual machines (VMs) in processor-based de2025
Processing data stream modification to reduce power effects during parallel proc2024
Power management circuit including on-board current-sense resistor and on-die cu2023
Processing data stream modification to reduce power effects during parallel proc2022
Ticket based request flow control2022
Bit inversion for data transmission2021
Enhanced dynamic memory management with intelligent current/power consumption mi2019
Enhanced dynamic memory management with intelligent current/power consumption mi2017
Monitoring and controlling bus ring performance2017
Methods and apparatus for improving performance of semaphore management sequence2016
Apparatus and methods employing variable clock gating hysteresis for a communica2016