Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Stacked integrated circuit with redundancy in die-to-die interconnects

Stacked integrated circuit with redundancy in die-to-die interconnects

US Patent 9236864 · Granted Jan 12, 2016

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Via configurable edge-combiner with duty cycle correction2025
Techniques for clock signal transmission in integrated circuits and interposers2024
Techniques for clock signal transmission in integrated circuits and interposers2022
Clock synchronization in multi-die field programmable gate array devices2020
Methods and apparatus for reducing power in clock distribution networks2017
Multi-layer distributed network2016
Multi-layer distributed network2016
Mask set for fabricating integrated circuits and method of fabricating integrate2016
Clock signal networks for structured ASIC devices2015
3D built-in self-test scheme for 3D assembly defect detection2014
3D built-in self-test scheme for 3D assembly defect detection2014
Systems including an I/O stack and methods for fabricating such systems2014