Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage

Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage

US Patent 9214233 · Granted Dec 15, 2015

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Memory and sense amplifying device thereof2024
Power-on read circuit2024
Semiconductor memory apparatus2024
Method for erasing memory cells in a flash memory device using a positive well b2023
Method for erasing memory cells in a flash memory device using a positive well b2023
Method for erasing memory cells in a flash memory device using a positive well b2023
Method for erasing memory cells in a flash memory device using a positive well b2021
Method for erasing memory cells in a flash memory device using a positive well b2021
Method for erasing memory cells in a flash memory device using a positive well b2021
Word line decoder circuit2019
Method for erasing memory cells in a flash memory device using a positive well b2019
Method for erasing memory cells in a flash memory device using a positive well b2019