Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Boundary latch and logic placement to satisfy timing constraints

Boundary latch and logic placement to satisfy timing constraints

US Patent 9098669 · Granted Aug 4, 2015

Estimated economic value: $5,566,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Detecting and modeling via during global routing2025
Cell-based pin access location generation2025
Restructuring algorithm for including user-specified clock instances in a post-C2025
Resistance and capacitance aware preferred layer trimming2025
Skewing level limited clock tree2025
Short net pin alignment for routing2025
Logic sharing maximization using non-unique matrix representation2025
Wire density-aware layer assignment2025
Timing-based layer assignment2025
Insertion delay and area tradeoff for buffering solution selection in clock tree2025
Insertion delay and area tradeoff for buffering solution selection in clock tree2025
Hierarchically-aware buffering for clock structures2025