Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage

Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage

US Patent 9034712 · Granted May 19, 2015

Estimated economic value: $4,677,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Electrostatic discharge protection devices2025
Electrically programmable fuse over lateral bipolar transistor2025
Electrically programmable fuse over crystalline semiconductor materials2025
High electron mobility transistor devices having a silicided polysilicon layer2025
High electron mobility transistor devices having a silicided polysilicon layer2025
Transistors for radio-frequency circuits and devices2025
Fin-based and bipolar electrostatic discharge devices2024
Bipolar transistors2024
Electrostatic discharge (ESD) device with improved turn-on voltage2024
High voltage electrostatic devices2024
High-voltage electrostatic discharge devices2024
High-voltage electrostatic discharge devices2024