Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › On-chip interferers for standards compliant jitter tolerance testing

On-chip interferers for standards compliant jitter tolerance testing

US Patent 9025693 · Granted May 5, 2015

Estimated economic value: $5,680,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System for and method of digital to analog conversion frequency distortion compe2024
Timing skew calibration in time-interleaved data converters in carrier aggregati2024
Apparatus, system, and method for auto-negotiation2019
High speed time-interleaved ADC gain offset and skew mitigation2016
High speed time-interleaved ADC gain offset and skew mitigation2016
Compensation for optical multi-path interference2016
Linearization of optical intensity modulation systems2015
Method and apparatus for reference-less repeater with digital control2015
Flexible ADC calibration technique using ADC capture memory2015
Flexible ADC calibration technique using ADC capture memory2015
Generalized transmit pre-coding for optical and backplane channels2015
Systems for high-speed backplane applications using pre-coding2015