Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and circuit of clock and data recovery with built in jitter tolerance test

Method and circuit of clock and data recovery with built in jitter tolerance test

US Patent 8989246 · Granted Mar 24, 2015

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Power amplifying circuit2017
Multi-channel timing recovery device2016
Circuit and method for clock data recovery and circuit and method for analyzing 2015
Equalizer and signal receiver thereof2015
Method and device of power saving for transmitting signals2015
Method and circuit of clock and data recovery with built in jitter tolerance tes2015
All digital serial link receiver with low jitter clock regeneration and method t2013
Marchand balun with air bridge2011
Three-dimensional balun2007