Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Packet processor configured for processing features directed by branch instruction with logical operator and two feature selector fields

Packet processor configured for processing features directed by branch instruction with logical operator and two feature selector fields

US Patent 8909906 · Granted Dec 9, 2014

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Self adapting driver for controlling datapath hardware elements2018
Network based service function chaining on top of rack switches2018
Method for layer 2 forwarding in a multi-node switch cluster2017
Method for real-time synchronization of ARP record in RSMLT cluster2017
Method for mapping packets to network virtualization instances2016
Method for abstracting datapath hardware elements2016
Method for thread reduction in a multi-thread packet processor2015
Method and apparatus for efficient loop instruction execution using bit vector s2015
Method and apparatus providing split multi link trunk (SMLT) for advanced techno2015
Method for heap management2015
Method for reducing processing latency in a multi-thread packet processor with a2015
Method for Media Access Control address learning and learning rate suppression2014