Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Process for manufacturing power integrated devices having surface corrugations, and power integrated device having surface corrugations

Process for manufacturing power integrated devices having surface corrugations, and power integrated device having surface corrugations

US Patent 8871594 · Granted Oct 28, 2014

Estimated economic value: $2,514,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Integrated circuit chip including a passivation nitride layer in contact with a 2025
Integrated circuit chip including a passivation nitride layer in contact with a 2024
Semiconductor structure with partially embedded insulation region and related me2022
Semiconductor die with buried capacitor, and method of manufacturing the semicon2021
Semiconductor structure with partially embedded insulation region2020
Method of manufacturing semiconductor devices and corresponding device2019
Semiconductor device with buried metallic region, and method for manufacturing t2018
Method for thermo-mechanical stress reduction in semiconductor devices and corre2018
Integrated device with raised locos insulation regions and process for manufactu2017
Electric contact structure having a diffusion barrier for an electronic device a2016
Method for manufacturing a transistor with self-aligned terminal contacts2016
Integrated device with raised locos insulation regions and process for manufactu2015