Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Apparatus and method for reducing interference signals in an integrated circuit using multiphase clocks

Apparatus and method for reducing interference signals in an integrated circuit using multiphase clocks

US Patent 8842766 · Granted Sep 23, 2014

Estimated economic value: $13,747,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Dynamic temperature calibration of ultrasonic transducers2025
Non-uniform multi-dimensional data access for radar data processing2025
Power efficient crest factor reduction2025
Coded ultrasonic sensing with staggered bursts2025
Infrastructure integrity checking2025
FFT engine having combined bit-reversal and memory transpose operations2025
Low power digital modes for duty-cycled integrated transceivers2024
Photodiode integrated with circuit2024
Bitonic sorting accelerator2024
Multi-dimensional FFT computation pipelined hardware architecture using Radix-3 2024
Ultrasonic transducer system and method using broadband system responses2024
Intermediate frequency amplifier with a configurable high-pass filter2024