Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Adjusting access times to memory cells based on characterized word-line delay and gate delay

Adjusting access times to memory cells based on characterized word-line delay and gate delay

US Patent 8787099 · Granted Jul 22, 2014

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Read accelerator circuit2023
Method and apparatus for selective write assist using shared boost capacitor2018
High bandwidth memory and glitch-less differential XOR2017
Bit line write assist for static random access memory architectures2015
Dual rail single-ended read data paths for static random access memories2015
Dual rail single-ended read data paths for static random access memories2015
Differential latch word line assist for SRAM2015
Address decoding circuits for reducing address and memory enable setup time2014
Address decoding circuits for reducing address and memory enable setup time2014
Content addressable memory data clustering block architecture2014
Adjusting bit-line discharge time in memory arrays based on characterized word-l2014
Adjusting bit-line discharge time in memory arrays based on characterized word-l2014