Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Vector instruction execution to load vector data in registers of plural vector units using offset addressing logic

Vector instruction execution to load vector data in registers of plural vector units using offset addressing logic

US Patent 8782376 · Granted Jul 15, 2014

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Communication between stacked die2025
Processing device for intermediate value scaling2025
Processing device for intermediate value scaling2025
Memory and routing module for use in a computer system2025
Stacked integrated circuit device2025
Multi-threaded barrel processor using shared weight registers in a common weight2025
Network computer with external memory2025
Computer system having a chip configured for memory attachment and routing2025
Computer system having a chip configured for memory attachment and routing2025
Network computer with two embedded rings2025
Scan testing in a processor2024
Instruction set2024