{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Performing a cyclic redundancy checksum operation responsive to a user-level instruction", "item": "https://www.patentleaderboard.com/patent/8769386"}]}
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Home › Performing a cyclic redundancy checksum operation responsive to a user-level instruction

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

US Patent 8769386 · Granted Jul 1, 2014

Estimated economic value: $13,029,000 ⓘ

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