Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Patterning method for fabrication of a semiconductor device

Patterning method for fabrication of a semiconductor device

US Patent 8592302 · Granted Nov 26, 2013

Estimated economic value: $3,520,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Transistor integration on a silicon-on-insulator substrate2024
Bipolar transistor structures with base having varying horizontal width and meth2024
Extended-drain metal-oxide-semiconductor devices with a silicon-germanium layer 2024
High voltage extended drain MOSFET (EDMOS) devices in a high-k metal gate (HKMG)2023
Integrated circuit structure with metal gate and metal field plate having coplan2022
Structure and method to provide conductive field plate over gate structure2022
Co-integrated high voltage (HV) and medium voltage (MV) field effect transistors2022
Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths an2022
Semiconductor device with novel spacer structures having novel configurations2021
Semiconductor device with interconnect to source/drain2021
Circuits constructed from stacked field-effect transistors2020
Asymmetric overlay mark for overlay measurement2020