Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Delay optimization during circuit design at layout level

Delay optimization during circuit design at layout level

US Patent 8549448 · Granted Oct 1, 2013

Estimated economic value: $3,560,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Fast synthesis of logical circuit design with predictive timing2024
Application-specific integrated circuit (ASIC) synthesis based on lookup table (2023
Satisfiability sweeping for synthesis2021
Scalable boolean methods in a modern synthesis flow2021
Robust exclusive sum-of-product (ESOP) refactoring2020
Integrated circuit (IC) optimization using Boolean resynthesis2020
Exact delay synthesis2019
Exact delay synthesis2018
Method for automatically determining probabilities associated with a Boolean fun1998
Method for automatically producing an implicit representation of the prime impli1995