Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for reducing Fermi-Level-Pinning in a non-silicon channel MOS device

Method for reducing Fermi-Level-Pinning in a non-silicon channel MOS device

US Patent 8524562 · Granted Sep 3, 2013

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method for interconnecting photovoltaic cells and photovoltaic cell assembly2025
Method of forming multiple-Vt FETS for CMOS circuit applications2023
Method of forming a thermal shield in a monolithic 3-d integrated circuit2023
Method of forming multi-threshold voltage devices and devices so formed2022
Semiconductor device including a repeater/buffer at upper metal routing layers a2022
Method of forming sacrificial self-aligned features for assisting die-to-die and2021
Method of forming isolation dielectrics for stacked field effect transistors (FE2021
Method of forming multiple-Vt FETs for CMOS circuit applications2021
Metal oxide semiconductor field effect transistor with crystalline oxide layer o2021
Method of forming multi-threshold voltage devices using dipole-high dielectric c2021
Removing an organic sacrificial material from a two-dimensional material2021
Charging prevention method and structure2021