Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Layout method for soft-error hard electronics, and radiation hardened logic cell

Layout method for soft-error hard electronics, and radiation hardened logic cell

US Patent 8468484 · Granted Jun 18, 2013

Assignee

No assignee recorded.

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Circuit architecture and layout for a voting interlocked logic cell2023
Circuit for low power, radiation hard logic cell2022
Soft error and radiation hardened sequential logic cell2015
Soft error resilient circuit design method and logic cells2015
Layout method for soft-error hard electronics, and radiation hardened logic cell2013
Soft error hard electronic circuit and layout2013
Power semiconductor component with transparent emitter and stop layer1997
Controlled turn-off power semiconductor device1997
Turn-off power semiconductor component, and also process for producing it1994