Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Highly parallel pipelined hardware architecture for integer and sub-pixel motion estimation

Highly parallel pipelined hardware architecture for integer and sub-pixel motion estimation

US Patent 8451897 · Granted May 28, 2013

Estimated economic value: $11,301,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Methods, systems, and computer-readable storage media for generating three-dimen2024
Methods, systems, and computer-readable storage media for generating three-dimen2024
Primary and auxiliary image capture devices for image processing and related met2022
Methods, systems, and computer-readable storage media for generating three-dimen2021
Methods, systems, and computer-readable storage media for generating three-dimen2021
Primary and auxiliary image capture devices for image processing and related met2021
Primary and auxiliary image capture devices for image processing and related met2019
Methods, systems, and computer-readable storage media for generating three-dimen2018
Methods, systems, and computer-readable storage media for generating three-dimen2018
Methods, systems, and computer-readable storage media for selecting image captur2017
Methods, systems, and computer-readable storage media for selecting image captur2017
Methods, systems, and computer-readable storage media for generating three-dimen2016