Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Two-chip co-design and co-optimization in three-dimensional integrated circuit net assignment

Two-chip co-design and co-optimization in three-dimensional integrated circuit net assignment

US Patent 8392870 · Granted Mar 5, 2013

Estimated economic value: $5,039,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Determining a density of through-silicon vias in integrated circuits2025
Broadband millimeter wave beam tracking method based on vehicle motion trajector2025
High-voltage cable insulation material continuous extrusion processing character2025
Service control method based on service cluster, electronic device and storage m2025
Chromogenic materials, methods of making chromogenic materials, and methods of u2025
Method of resource adjustment for service cluster, electronic device and storage2025
Deaminase-based RNA sensors2025
Image processing method and apparatus2024
Micro-LED burn-in statistics and compensation systems and methods2024
Markerless motion capture of hands with multiple pose estimation engines2024
Inverse pixel burn-in compensation systems and methods2024
Pixel drive circuitry burn-in compensation systems and methods2024