Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › High density high reliability memory module with power gating and a fault tolerant address and command bus

High density high reliability memory module with power gating and a fault tolerant address and command bus

US Patent 8381064 · Granted Feb 19, 2013

Estimated economic value: $3,959,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

High reliability memory module with a fault tolerant address and command bus2013
High density high reliability memory module with power gating and a fault tolera2011
High reliability memory module with a fault tolerant address and command bus2010
Memory device with programmable receivers to improve performance2010
Processor memory array having memory macros for relocatable store protect keys2009
High density high reliability memory module with a fault tolerant address and co2009
High reliability memory module with a fault tolerant address and command bus2008
High reliability memory module with a fault tolerant address and command bus2008
High reliability memory module with a fault tolerant address and command bus2008
High reliability memory module with a fault tolerant address and command bus2007
Memory interface with programable clock to output time based on wide range of re2003
Captured synchronous DRAM fails in a working environment2002