Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Identifying an optimized test bit pattern for analyzing electrical communications channel topologies

Identifying an optimized test bit pattern for analyzing electrical communications channel topologies

US Patent 8327196 · Granted Dec 4, 2012

Estimated economic value: $3,998,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Fiber weave in a printed circuit board substrate2025
Noise cancellation in low-speed signals2025
Signal speed increase in a connector wipe2025
System and method to maintain signal integrity between multiple signal paths con2025
Reflective cancellations in a connector wipe of a surface mount connector2025
Impedance tuning of microstrip traces2025
Systems and methods for testing cabled interconnects under mechanical stress2025
Systems and methods for testing cabled interconnects under mechanical stress2025
On-die termination optimization2025
Reflective cancellations in a connector wipe2025
Printed circuit board with reduced via striping2025
Integrated thermal-electrical co-simulation2025