Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions

Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions

US Patent 8236653 · Granted Aug 7, 2012

Estimated economic value: $733,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Device structure and manufacturing method using HDP deposited source-body implan2021
Integrated isolation capacitance structure2020
Top drain LDMOS2018
Device structure and manufacturing method using HDP deposited source-body implan2017
Method of fabrication and device configuration of asymmetrical DMOSFET with scho2016
Method of fabrication and device configuration of asymmetrical DMOSFET with scho2016
Dual gate oxide trench MOSFET with channel stop trench2015
Top drain LDMOS2015
Device structure and manufacturing method using HDP deposited source-body implan2015
Method of making MOSFET integrated with schottky diode with simplified one-time 2015
Fabrication of trench DMOS device having thick bottom shielding oxide2015
Dual gate oxide trench MOSFET with channel stop trench2014