Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory units with packet processor for decapsulating read write access from and encapsulating response to external devices via serial packet switched protocol interface

Memory units with packet processor for decapsulating read write access from and encapsulating response to external devices via serial packet switched protocol interface

US Patent 8234483 · Granted Jul 31, 2012

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Identity recognition utilizing face-associated body characteristics2025
Conductive protrusion assembly for an evaporator of an ice-making machine2025
Remotely programmable multi mode bidirectional power converter2023
System and method for a multi purpose bidirectional power converter2021
Multi protocol communication switch apparatus2019
Processor apparatus with programmable multi port serial communication interconne2018
Bidirectional multimode power converter2017
Protocol translation method and bridge device for switched telecommunication and2016
Plural processing cores communicating packets with external port via parallel bu2014
Serial memory and IO access architecture and system for switched telecommunicati2014
Omni-protocol engine for reconfigurable bit-stream processing in high-speed netw2012
Telecommunication and computing platforms with serial packet switched integrated2012