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Home › Utilizing a bidding model in a microparallel processor architecture to allocate additional registers and execution units for short to intermediate stretches of code identified as opportunities for microparallelization

Utilizing a bidding model in a microparallel processor architecture to allocate additional registers and execution units for short to intermediate stretches of code identified as opportunities for microparallelization

US Patent 8230410 · Granted Jul 24, 2012

Estimated economic value: $4,383,000 ⓘ

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