Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device

Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device

US Patent 8138578 · Granted Mar 20, 2012

Estimated economic value: $14,822,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Low leakage FINFETs2013
Electrostatic discharge (ESD) protection structure and a circuit using the same2010
LOCOS self-aligned twin well with a co-planar silicon surface2010
LOCOS self-aligned twin well with a co-planar silicon surface2010
Method and materials to control doping profile in integrated circuit substrate m2009
Method for forming a self-aligned twin well region with simplified processing2009
Method for forming a self-aligned twin well region with simplified processing2009
Method and system for creating self-aligned twin wells with co-planar surfaces i2009
Method and system for creating self-aligned twin wells with co-planar surfaces i2009
Polish stop and sealing layer for manufacture of semiconductor devices with deep2008
DMOS device with sealed channel processing2008
Electrostatic discharge (ESD) protection structure and a circuit using the same2008