Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Structure and method to optimize computational efficiency in low-power environments

Structure and method to optimize computational efficiency in low-power environments

US Patent 8122273 · Granted Feb 21, 2012

Estimated economic value: $5,017,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Isolation regions for charge collection and removal2024
Integrated circuit structure with fluorescent material, and related methods2024
Anti-tamper x-ray blocking package2022
Method and related structure to authenticate integrated circuit with authenticat2022
Enabling of functional logic in IC using thermal sequence enabling test2022
Active attack prevention for secure integrated circuits using latchup sensitive 2021
Active x-ray attack prevention device2021
Sensing circuits for charge trap transistors2021
System and method to drive logic circuit with non-deterministic clock edge varia2021
Transition once multiplexer circuit2020
IC wafer for identification of circuit dies after dicing2020
Tamper detection for a chip package2020