{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Scalable interface for a memory array", "item": "https://www.patentleaderboard.com/patent/8099562"}]}
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Home › Scalable interface for a memory array

Scalable interface for a memory array

US Patent 8099562 · Granted Jan 17, 2012

Estimated economic value: $12,258,000 ⓘ

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