Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of testing an integrity of a material layer in a semiconductor structure

Method of testing an integrity of a material layer in a semiconductor structure

US Patent 8058081 · Granted Nov 15, 2011

Estimated economic value: $6,438,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Integral gas-introduction and stirring unit for gas-liquid reactors2025
Method including a formation of a diffusion barrier and semiconductor structure 2018
Metal line layout based on line shifting2018
Method comprising applying an external mechanical stress to a semiconductor stru2016
Methods of forming metal nitride materials2015
Methods for fabricating integrated circuits including barrier layers for interco2015
Method including an etching of a portion of an interlayer dielectric in a semico2015
Method for detecting defects in a diffusion barrier layer2015
Multi-step deposition control2013
Technique for forming metal lines in a semiconductor by adapting the temperature2013
Technique for forming metal lines in a semiconductor by adapting the temperature2013
Method of forming an alloy in an interconnect structure to increase electromigra2012