Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methods and apparatus for layout of multi-layer circuit substrates

Methods and apparatus for layout of multi-layer circuit substrates

US Patent 7996806 · Granted Aug 9, 2011

Estimated economic value: $3,840,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Disk drive thermal performance testing devices and methods thereof2018
Timestamp correction in a multi-lane communication link with skew2015
Feedback controller having multiple feedback paths2011
Gain control circuit2010
Low voltage synchronous oscillator for DC-DC converter2010
Fuse cell and method for programming the same2009
Differential receiver with wide input common mode range and low duty cycle disto2008
Phase-locked loop (PLL) device and method for entering a test mode without a ded2008
Voltage translator circuit formed using low voltage transistors2006
Pin-to-pin ESD-protection structure having cross-pin activation2004
ESD-isolation circuit driving gate of bus-switch transistor during ESD pulse bet2004
Reduced clock-skew in a multi-output clock driver by selective shorting together2003