Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System and method for random defect yield simulation of chip with built-in redundancy

System and method for random defect yield simulation of chip with built-in redundancy

US Patent 7984399 · Granted Jul 19, 2011

Estimated economic value: $4,588,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Context-aware circuit design layout construct2024
Model-based simulation result predictor for circuit design2023
Relative placement by application of layered abstractions2023
System and method for device placement2022
EDA CAA with learning phase2020
Methods, systems, and computer program products for implementing an electronic d2020
Physical to virtual scheduling system and method2020
Method, system, and computer program product for implementing routing aware plac2019
Method and system for performing incremental post layout simulation with layout 2019
Method, system, and computer program product for implementing track patterns for2019
Methods, systems, and articles of manufacture for interactively implementing phy2018
Methods, systems, and computer program product for implementing DRC clean multi-2018