Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Verifying configuration memory of a programmable logic device

Verifying configuration memory of a programmable logic device

US Patent 7912693 · Granted Mar 22, 2011

Estimated economic value: $8,957,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Interoperable containerization for feature framework2025
Boundary logic interface2020
System and method for testing of interconnects in a programmable logic device2009
System and method for testing of interconnects in a programmable logic device2009
Dummy block replacement for logic simulation2008
Programmable logic device with decryption and structure for preventing design re2006
Bitstream for configuring a PLD with encrypted design data2006
Partially encrypted bitstream method2006
Programmable logic device with method of preventing readback2005
Programmable logic device with decryption algorithm and decryption key2005