Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning

Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning

US Patent 7895545 · Granted Feb 22, 2011

Estimated economic value: $3,876,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Timing-aware and simultaneous optimization of latch clustering and placement in 2025
Rule check heatmap prediction2025
Short net pin alignment for routing2025
Autonomous driving evaluation using data analysis2025
Power staple avoidance for routing via reduction2025
Technology-independent line end routing2024
Fast independent checker for extreme ultraviolet (EUV) routing2024
Double-sided two-way ranging protocol based on composite, ultrasonic tones2023
Infer text classifiers for large text collections2023
Region-based layout routing2023
Autonomous driving evaluation using data analysis2023
Sweepline triangulation for spanning graphs2023