Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Reading and writing a memory element within a programmable processing element in a plurality of modes

Reading and writing a memory element within a programmable processing element in a plurality of modes

US Patent 7865695 · Granted Jan 4, 2011

Estimated economic value: $15,011,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method and apparatus for a finite impulse response filter2014
Method and apparatus for a finite impulse response filter2014
Reconfigurable networked processing elements partial differential equations syst2013
Heterogeneous computer architecture based on partial reconfiguration2013
Datapipe synchronization device2011
Datapipe synchronization device2011
Noise-driven recovery of a digital pulse stream2011
Reconfigurable communications infrastructure for ASIC networks2011
Reconfigurable communications infrastructure for ASIC networks2011
CPU datapipe architecture with crosspoint switch2011
Linear combiner weight memory2010
Linear combiner weight memory2010