Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory controller and method for operating a memory controller having an integrated bit error rate circuit

Memory controller and method for operating a memory controller having an integrated bit error rate circuit

US Patent 7853837 · Granted Dec 14, 2010

Estimated economic value: $19,506,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Scalable architecture for reduced cycles across SOC2025
Memory controllers, systems, and methods supporting multiple request modes2025
Scalable architecture for reduced cycles across SOC2024
Memory controllers, systems, and methods supporting multiple request modes2023
Periodic calibration for communication channels by drift tracking2023
Communication channel calibration for drift conditions2023
Memory controllers, systems, and methods supporting multiple request modes2022
Periodic calibration for communication channels by drift tracking2022
Memory component with pattern register circuitry to provide data patterns for ca2022
Communication channel calibration for drift conditions2021
Integrated mixed-signal RF transceiver with ADC, DAC, and DSP and high-bandwidth2021
Periodic calibration for communication channels by drift tracking2020