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Home › Method of fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channel

Method of fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channel

US Patent 7795112 · Granted Sep 14, 2010

Estimated economic value: $3,726,000 ⓘ

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