Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Scheduler design to optimize system performance using configurable acceleration engines

Scheduler design to optimize system performance using configurable acceleration engines

US Patent 7752592 · Granted Jul 6, 2010

Estimated economic value: $3,063,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Nanosecond accuracy of timestamping by leveraging alignment marker and method fo2020
Nanosecond accuracy under precision time protocol for ethernet by using high acc2018
Energy efficient high-speed link and method to maximize energy savings on the en2017
Forward error correction synchronization2016
Programmable direct memory access controller having pipelined and sequentially c2011
Access table lookup for bus bridge2011
Efficient, flexible motion estimation architecture for real time MPEG2 compliant2003
Real-time variable bit rate encoding of video sequence employing statistics2000
Dual prime motion estimation system and method2000
Apparatus and method for detecting end of serial bit stream1999
High speed asynchronous serial to parallel data converter1998
Scalable MPEG2 compliant video encoder1998