Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Configuring structured ASIC fabric using two non-adjacent via layers

Configuring structured ASIC fabric using two non-adjacent via layers

US Patent 7692309 · Granted Apr 6, 2010

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Scalable security for cryptographic ledgers via dynamic and unpredictable change2024
Scalable security for cryptographic ledgers via dynamic and unpredictable change2023
Scalable security for cryptographic ledgers via dynamic and unpredictable change2022
Via configurable architecture for customization of analog circuitry in a semicon2011
Using selectable in-line inverters to reduce the number of inverters in a semico2011
Via configurable architecture for customization of analog circuitry in a semicon2009
Configurable integrated circuit capacitor array using via mask layers2009
Logic array devices having complex macro-cell architecture and methods facilitat2009
VIA configurable architecture for customization of analog circuitry in a semicon2008
Creating high-drive logic devices from standard gates with minimal use of custom2008
Configurable integrated circuit capacitor array using via mask layers2008
Customization of structured ASIC devices using pre-process extraction of routing2008