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Home › Compact CMOS ESD layout techniques with either fully segmented salicide ballasting (FSSB) in the source and/or drain regions

Compact CMOS ESD layout techniques with either fully segmented salicide ballasting (FSSB) in the source and/or drain regions

US Patent 7646063 · Granted Jan 12, 2010

Estimated economic value: $19,559,000 ⓘ

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