Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory hub architecture having programmable lane widths

Memory hub architecture having programmable lane widths

US Patent 7596675 · Granted Sep 29, 2009

Estimated economic value: $10,038,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Memory hub architecture having programmable lane widths2016
Memory hub architecture having programmable lane widths2016
Memory hub architecture having programmable lane widths2014
Memory hub architecture having programmable lane widths2014
Memory hub architecture having programmable lane widths2011
Memory hub architecture having programmable lane widths2011
Memory hub architecture having programmable lane widths2008
Memory hub architecture having programmable lane widths2008
Mechanism to expand address space of a serial bus2003
Method and system for increasing the performance of constant angular velocity CD2001