Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Reducing bit line leakage current in non-volatile memories

Reducing bit line leakage current in non-volatile memories

US Patent 7586787 · Granted Sep 8, 2009

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Apparatus for non-volatile random access memory stacks2025
Formation of stacked lateral semiconductor devices and the resulting structures2024
Non-volatile dynamic random access memory2024
Apparatus for non-volatile random access memory stacks2024
Multi-layer random access memory and methods of manufacture2023
Three-dimensional array architecture for resistive change element arrays and met2022
Multi-layer horizontal thyristor random access memory and peripheral circuitry2022
Multi-layer thyristor random access memory with silicon-germanium bases2022
High density vertical thyristor memory cell array with improved isolation2022
System idle time reduction methods and apparatus2022
3D stacked high-density memory cell arrays and methods of manufacture2022
Thyristor volatile random access memory and methods of manufacture2021