Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Circuit-level memory and combinational block modeling

Circuit-level memory and combinational block modeling

US Patent 7516060 · Granted Apr 7, 2009

Assignee

No assignee recorded.

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Using co-located secondary devices to protect against cookie theft2025
Systems and methods to deliver content during client authentication process in a2025
Privacy-preserving activity aggregation mechanism2025
Systems and methods to evaluate client device trust in a distributed computing s2025
Systems and methods to deliver content during client authentication process in a2023
Access control technology for peer-to-peer sharing2021
Providing online media content via a satellite broadcast system2020
Access control technology for peer-to-peer sharing2019
Method for piecewise hierarchical sequential verification2013
Circuit-level memory and combinational block modeling2005
Analysis of Rheed data from rotating substrates1993