Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Systems and methods for controlling clock signals during scan testing integrated circuits

Systems and methods for controlling clock signals during scan testing integrated circuits

US Patent 7500165 · Granted Mar 3, 2009

Estimated economic value: $6,197,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Integrated circuit allowing to test a power management unit based on or more con2014
Control of tristate buses during scan test2012
Protecting data on integrated circuit2011
Methods and computer program products for debugging clock-related scan testing f2009
Debug method for mismatches occurring during the simulation of scan patterns2009
Memory bypass with support for path delay test2008
System and method for clock domain grouping using data path relationships2008
Methods for debugging scan testing failures of integrated circuits2008
Systems and methods for scan test access using bond pad test access circuits2006
Scan testing mode control of gated clock signals for flip-flops2006
Methodology for selectively testing portions of an integrated circuit2006
Scan testing mode control of gated clock signals for memory devices2006