Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Delay stage-interweaved analog DLL/PLL

Delay stage-interweaved analog DLL/PLL

US Patent 7489568 · Granted Feb 10, 2009

Estimated economic value: $1,650,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Adaptive selection of a configuration-dependent operand2025
DRAM row copy2025
Memory die interconnections to physical layer interfaces2025
Apparatuses and methods including multilevel command and address signals2025
Bank-level self-refresh2025
Voltage generation and regulation across multiple dies2025
Die-based rank management2025
Automated error correction with memory refresh2025
Adaptive wordline refresh2025
Dynamic address scramble2025
Write timing compensation2025
Asymmetric read-write sequence for interconnected dies2025