Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibility

Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibility

US Patent 7482851 · Granted Jan 27, 2009

Estimated economic value: $4,993,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Circuit for detecting structural defects in an integrated circuit chip, methods 2017
Optimization of integrated circuit physical design2017
Verifying partial good voltage island structures2015
Circuit for detecting structural defects in an integrated circuit chip, methods 2015
Method and device for selectively adding timing margin in an integrated circuit2013
Test path selection and test program generation for performance testing integrat2013
Method and device for selectively adding timing margin in an integrated circuit2013
Disposition of integrated circuits using performance sort ring oscillator and pe2013
Method and device for selectively adding timing margin in an integrated circuit2013
Dense register array for enabling scan out observation of both L1 and L2 latches2013
Dense register array for enabling scan out observation of both L1 and L2 latches2013
Microcontroller for logic built-in self test (LBIST)2013