Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and system for layout versus schematic validation of integrated circuit designs

Method and system for layout versus schematic validation of integrated circuit designs

US Patent 7480878 · Granted Jan 20, 2009

Estimated economic value: $5,499,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Waiver mechanism for physical verification of system designs2011
Unified layer stack architecture2010
N cell height decoupling circuit2010
Method of automating place and route corrections for an integrated circuit desig2007
Incremental dummy metal insertions2007
Method of implementing an engineering change order in an integrated circuit desi2007
Method and computer program for verifying an incremental change to an integrated2007
Method of early physical design validation and identification of texted metal sh2006
Method of early physical design validation and identification of texted metal sh2006
Method of partitioning an integrated circuit design for physical design verifica2006
Web based OLA memory generator2006
Method and apparatus for implementing engineering change orders2006