Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Loop-back method for measuring the interface timing of semiconductor devices with the aid of signatures and/or parity methods

Loop-back method for measuring the interface timing of semiconductor devices with the aid of signatures and/or parity methods

US Patent 7398444 · Granted Jul 8, 2008

Estimated economic value: $560,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Mitigating voltage overshoot at a transmission line2025
Multi-voltage operation for driving a multi-mode channel2025
Temperature-dependent refresh operations2025
Configuring command/address channel for memory2025
Configuring command/address channel for memory2025
Channel modulation for a memory device2025
Channel modulation for a memory device2025
Activate commands for memory preparation2025
Dynamic control of error management and signaling2025
Dynamic control of error management and signaling2025
Controlled heating of a memory device2025
Controlled heating of a memory device2025