Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for simultaneous fabrication of a nanocrystal and non-nanocrystal device

Method for simultaneous fabrication of a nanocrystal and non-nanocrystal device

US Patent 7391081 · Granted Jun 24, 2008

Estimated economic value: $4,747,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Non-thermally annealed doped semiconductor material and methods related thereto2009
Low voltage non-volatile memory cell with electrically transparent control gate2009
Contactless nonvolatile memory array2008
Self-aligned non-volatile memory cell2008
Method of making nonvolatile transistor pairs with shared control gate2008
Method of making EEPROM transistor pairs for block alterable memory2008
Self-aligned nanometer-level transistor defined without lithography2008
Method of fabricating a semiconductor device having a toroidal-like junction2008
Ultrascalable vertical MOS transistor with planar contacts2008
Non-volatile nanocrystal memory transistors using low voltage impact ionization2007
Non-volatile memory array with simultaneous write and erase feature2007
Memory cell with reduced size and standby current2007